The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2023

Filed:

Dec. 17, 2019
Applicant:

Wuhan Xinxin Semiconductor Manufacturing Co., Ltd., Hubei, CN;

Inventors:

Fan Yang, Hubei, CN;

Sheng Hu, Hubei, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14687 (2013.01); H01L 27/1463 (2013.01); H01L 27/1464 (2013.01); H01L 27/14632 (2013.01); H01L 27/14636 (2013.01);
Abstract

A semiconductor device and a method of fabricating thereof are disclosed. The method of fabricating a semiconductor device includes: forming a trench fill structure in a substrate in a pixel area; covering a buffer dielectric layer over a surface of the substrate in the pixel area, the buffer dielectric layer burying the trench fill structure; etching the buffer dielectric layer to form a first opening, which exposes at least a portion of the substrate surrounding sidewalls of a top of the trench fill structure and/or at least a portion of the top of the trench fill structure; and forming a metal grid layer on the buffer dielectric layer, wherein the metal grid layer fills the first opening and is electrically connected to the exposed portion of the substrate and/or the exposed portion of the trench fill structure. The present invention provides a technical solution that brings the metal grid layer into electrical connection with the exposed portion of the substrate and/or part of the top of the trench fill structure, thus allowing optimization or amelioration of the semiconductor device's electrical performance.


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