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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11791327 B1

PDFFull Text
Date of Patent:
Oct. 17, 2023

Filed:

Aug. 25, 2021

Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof

Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Kwang-Ho Kim, Pleasanton, CA (US);

Masaaki Higashitani, Cupertino, CA (US);

Fumiaki Toyama, Cupertino, CA (US);

Akio Nishida, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:

THE MARBURY LAW GROUP PLLC

Primary Examiner:

Hsien Ming Lee

Int. Cl.
CPC ...
H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/50 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10B 43/50 (2023.02); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/8083 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/41 (2023.02);
Abstract

A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.

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