The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2023

Filed:

Jun. 02, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Jerry Chang-Jui Kao, Taipei, TW;

Hui-Zhong Zhuang, Kaohsiung, TW;

Li-Chung Hsu, Hsinchu, TW;

Sung-Yen Yeh, Pingtung County, TW;

Yung-Chen Chien, Kaohsiung, TW;

Jung-Chan Yang, Taoyuan, TW;

Tzu-Ying Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/822 (2006.01); H01L 21/48 (2006.01); H01L 23/535 (2006.01); H01L 23/50 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8221 (2013.01); H01L 21/4828 (2013.01); H01L 23/50 (2013.01); H01L 23/535 (2013.01);
Abstract

A system includes a non-transitory storage medium encoded with a set of instructions and a processor. The processor is configured to execute the set of instructions. The set of instructions is configured to cause the processor to: obtain, based on a netlist of a circuit, values each corresponding to one of transistors included in the circuit; compare the values with a threshold value; in response to a comparison, generate an adjusted netlist of the circuit by adding redundant transistors; and determine, based on the adjusted netlist, one of layout configurations for the circuit. The layout configurations include first cell rows each having a first row height and second cell rows each having a second row height different from the first row height.


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