The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2023

Filed:

Apr. 26, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Robert B. Eisenhuth, Boulder, CO (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); H03M 13/15 (2006.01); G06F 11/00 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1076 (2013.01); G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); H03M 13/152 (2013.01); H03M 13/1515 (2013.01);
Abstract

Methods, systems, and devices for error correction for internal read operations are described. In some memory systems, a memory device may perform an internal read operation, in which the memory device reads data internal to the memory device (e.g., without sending the data to a memory system controller). To detect and correct errors during an internal read operation, the memory device may use an error control circuit on a memory die. The error control circuit on the memory die may operate on the same codeword, including the same data and same parity bits, as an error control circuit at the memory system controller, effectively reusing the stored parity bits for host read operations and internal read operations. To reduce the decoding overhead at the memory device, the error control circuit on the memory die may support detecting fewer errors than the error control circuit at the memory system controller.


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