The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2023

Filed:

Jun. 16, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Kuo-Cheng Chiang, Zhubei, TW;

Ching-Wei Tsai, Hsinchu, TW;

Chi-Wen Liu, Hsinchu, TW;

Ying-Keung Leung, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 29/66 (2006.01); H01L 29/165 (2006.01); H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 21/283 (2006.01); H01L 29/78 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/02271 (2013.01); H01L 21/283 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01); H01L 21/76834 (2013.01); H01L 21/76897 (2013.01);
Abstract

Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.


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