The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2023

Filed:

Aug. 20, 2021
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Francois Hebert, San Mateo, CA (US);

Handoko Linewih, , SG;

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/84 (2006.01); H01L 27/085 (2006.01); H01L 29/872 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/84 (2013.01); H01L 27/085 (2013.01); H01L 29/872 (2013.01);
Abstract

Structures including III-V compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region, and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer contains a III-V compound semiconductor material, and the second semiconductor layer contains silicon. A first device structure includes a gate structure on the first semiconductor layer, and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.


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