The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2023

Filed:

Dec. 20, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Eah Loon Alan Chuah, Tanjung Tokong, MY;

Ting Ting Au, Bayan Lepas, MY;

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/50 (2006.01); H01L 23/522 (2006.01); H03K 19/00 (2006.01); H01L 23/62 (2006.01); H01L 21/768 (2006.01); H01L 21/027 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/0274 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/525 (2013.01); H01L 23/62 (2013.01); H03K 19/0005 (2013.01);
Abstract

An integrated circuit device with a single via layer, in which the via layer includes selectable via sites and/or jumpers. The selectable via sites and/or placement of jumpers may be used to configure and interconnect components and circuitry between distinct layers of multilayer circuits. In some implementations, selectively enabling via sites by filling via openings and/or using jumpers may implement a single-ended termination circuit with a first via configuration, a Thevenin termination circuit with a second via configuration, and/or a differential termination circuit with a third configuration.


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