The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2023

Filed:

Mar. 09, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Joseph Thomas Pawlowski, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); H04L 47/10 (2022.01); G06F 13/18 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1075 (2013.01); G06F 13/16 (2013.01); G06F 13/18 (2013.01); H04L 47/10 (2013.01);
Abstract

Methods, systems, and devices for a multi-port storage-class memory interface are described. A memory controller of the storage-class memory subsystem may receive, from a host device, a request associated with host addresses. The memory controller may generate interleaved addresses with a low latency based on the host addresses. The interleaved addresses parallelize processing of the request utilizing a set of memory media ports. Each memory media port of the set of memory media port may operate independent of each other to obtain a desired aggregated data transfer rate and a memory capacity. The interleaved address may leave no gaps in memory space. The memory controller may control a wear-leveling operation to distribute access operations across one or more zones of the memory media port.


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