The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2023
Filed:
Jun. 14, 2022
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Guo-Huei Wu, Hsinchu, TW;
Pochun Wang, Hsinchu, TW;
Chih-Liang Chen, Hsinchu, TW;
Li-Chun Tien, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); G06F 30/392 (2020.01); G06F 30/31 (2020.01); H01L 21/8238 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); G06F 111/02 (2020.01);
U.S. Cl.
CPC ...
H01L 27/0922 (2013.01); G06F 30/31 (2020.01); G06F 30/392 (2020.01); H01L 21/823871 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); G06F 2111/02 (2020.01);
Abstract
A semiconductor device includes a buried communication (com) conductor (BC) CFET including: first and second active regions arranged in a stack according to CFET-type configuration; a first layer of metallization (M_1st layer) over the stack which includes first conductors configured for data or control signals (communication (com) conductors), and power grid (PG) conductors; and a layer of metallization (M_B layer) below the stack and which includes second com conductors.