The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2023

Filed:

Feb. 22, 2022
Applicant:

Ceremorphic, Inc., San Jose, CA (US);

Inventors:

Subba Reddy Kallam, Sunnyvale, CA (US);

Partha Sarathy Murali, Sunnyvale, CA (US);

Venkat Mattela, San Jose, CA (US);

Venkata Siva Prasad Pulagam, Segunderabad, IN;

Assignee:

Ceremorphic, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/52 (2006.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3836 (2013.01); G06F 9/30123 (2013.01); G06F 9/30145 (2013.01); G06F 9/3802 (2013.01); G06F 9/3851 (2013.01); G06F 9/52 (2013.01);
Abstract

A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.


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