The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Oct. 21, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Bo-Feng Young, Taipei, TW;

Sai-Hooi Yeong, Zhubei, TW;

Chi On Chui, Hsinchu, TW;

Chun-Chieh Lu, Taipei, TW;

Yu-Ming Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/27 (2023.01); G11C 7/18 (2006.01); G11C 8/14 (2006.01); H10B 41/10 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H10B 41/27 (2023.02); G11C 7/18 (2013.01); G11C 8/14 (2013.01); H10B 41/10 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02);
Abstract

In an embodiment, a method includes forming a multi-layer stack including alternating layers of an isolation material and a semiconductor material, patterning the multi-layer stack to form a first channel structure in a first region of the multi-layer stack, where the first channel structure includes the semiconductor material, depositing a memory film layer over the first channel structure, etching a first trench extending through a second region of the multi-layer stack to form a first dummy bit line and a first dummy source line in the second region, where the first dummy bit line and first dummy source line each include the semiconductor material, and replacing the semiconductor material of the first dummy bit line and the first dummy source line with a conductive material to form a first bit line and a first source line.


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