The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Dec. 05, 2022
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Lars Liebmann, Mechanicsville, NY (US);

Jeffrey Smith, Clifton Park, NY (US);

Daniel Chanemougame, Niskayuna, NY (US);

Paul Gutwin, Williston, VT (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1029 (2013.01); H01L 29/0665 (2013.01); H01L 29/66818 (2013.01); H01L 29/785 (2013.01);
Abstract

A semiconductor device includes a first field-effect transistor positioned over a substrate, a second field-effect transistor stacked over the first field-effect transistor, a third field-effect transistor stacked over the second field-effect transistor, and a fourth field-effect transistor stacked over the third field-effect transistor. A bottom gate structure is disposed around a first channel structure of the first field-effect transistor and positioned over the substrate. An intermediate gate structure is disposed over the bottom gate structure and around a second channel structure of the second field-effect transistor and a third channel structure of the third field-effect transistor. A top gate structure is disposed over the intermediate gate structure and around a fourth channel structure of the fourth field-effect transistor. An inter-level contact is formed to bypass the intermediate gate structure from a first side of the intermediate gate structure, and arranged between the bottom gate structure and the top gate structure.


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