The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Dec. 02, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Harshitha Vishwanath, Bangalore, IN;

Renukprasad Hiremath, Portland, OR (US);

Sukru Yemenicioglu, Portland, OR (US);

Ranjith Kumar, Beaverton, OR (US);

Ruth Amy Brain, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 27/0207 (2013.01);
Abstract

Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a substrate, and a cell on the substrate. In an embodiment, the cell comprises a plurality of transistors over the substrate, and a first metal layer over the plurality of transistors. In an embodiment, the first metal layer comprises a first power line, wherein a width of the first power line is entirely within the cell, a second power line, wherein a width of the second power line is entirely within the cell, and a plurality of signal lines between the first power line and the second power line.


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