The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Aug. 12, 2021
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Evelyn Napetschnig, Diex, AT;

Jens Brandenburg, Munich, DE;

Christoffer Erbert, St. Magdalen, AT;

Joachim Hirschler, Villach, AT;

Oliver Humbel, Maria Elend, AT;

Thomas Rupp, Faak am See, AT;

Carsten Schaeffer, Annenheim, AT;

Julia Zischang, Villach, AT;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 23/00 (2006.01); H01L 23/485 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 23/485 (2013.01); H01L 23/53219 (2013.01); H01L 23/53233 (2013.01);
Abstract

A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.


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