The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Mar. 28, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Benben Li, Boise, ID (US);

Akira Goda, Setagaya, JP;

Ramey M. Abdelrahaman, Boise, ID (US);

Ian C. Laboriante, Boise, ID (US);

Krishna K. Parat, Palo Alto, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 11/408 (2006.01); G11C 8/08 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/60 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 51/20 (2023.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
G11C 16/0475 (2013.01); G11C 8/08 (2013.01); G11C 11/4087 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/60 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 51/20 (2023.02); H10B 63/84 (2023.02); H10N 70/883 (2023.02); G11C 16/0483 (2013.01);
Abstract

Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.


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