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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11763061 B1

PDFFull Text
Date of Patent:
Sep. 19, 2023

Filed:

Jul. 28, 2022

Method of making semiconductor device and semiconductor device

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Jen Chen, Hsinchu, TW;

Ling-Sung Wang, Hsinchu, TW;

I-Shan Huang, Hsinchu, TW;

Chan-Yu Hung, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

Hauptman Ham, LLP

Primary Examiner:

Alia Sabur

Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/423 (2006.01); G06F 30/392 (2020.01); H01L 27/02 (2006.01); G03F 1/70 (2012.01); G03F 1/36 (2012.01); H01L 27/092 (2006.01); G06F 30/39 (2020.01); G06F 30/398 (2020.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 21/027 (2006.01); H01L 21/8234 (2006.01); G06F 119/18 (2020.01); G06F 111/20 (2020.01); G03F 1/30 (2012.01); G03F 1/32 (2012.01); G03F 7/20 (2006.01); H10B 10/00 (2023.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G03F 1/36 (2013.01); G03F 1/70 (2013.01); G06F 30/39 (2020.01); G06F 30/398 (2020.01); H01L 21/28123 (2013.01); H01L 27/0207 (2013.01); H01L 27/0886 (2013.01); H01L 27/092 (2013.01); H01L 29/4238 (2013.01); G03F 1/30 (2013.01); G03F 1/32 (2013.01); G03F 7/2002 (2013.01); G03F 7/2037 (2013.01); G06F 2111/20 (2020.01); G06F 2119/18 (2020.01); H01L 21/0274 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 27/0924 (2013.01); H10B 10/12 (2023.02);
Abstract

A method of making a semiconductor structure includes forming a plurality of gate electrodes over a plurality of active regions. The method further includes increasing a width of a portion of each of the plurality of gate electrodes between adjacent active regions of the plurality of active regions, wherein increasing the width of the portion of each of the plurality of gate electrodes comprises increasing the width of less than an entirety of each of the plurality of gate electrodes between the adjacent active regions. The method further includes removing a central region of each of the plurality of gate electrodes, wherein the central region has the increased width, and removing the central region comprises removing less than an entirety of the portion of each of the plurality of gate electrodes.

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