The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2023

Filed:

Nov. 08, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Charles Leon Arvin, Poughkeepsie, NY (US);

Bhupender Singh, Fishkill, NY (US);

Shidong Li, Hopewell Junction, NY (US);

Chris Muzzy, Burlington, VT (US);

Thomas Anthony Wassick, LaGrangeville, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 21/56 (2006.01); H01L 23/64 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); H01L 21/56 (2013.01); H01L 23/3121 (2013.01); H01L 23/5386 (2013.01); H01L 23/642 (2013.01); H01L 24/13 (2013.01); H01L 25/50 (2013.01); H01L 2224/13147 (2013.01);
Abstract

A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.


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