The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 12, 2023
Filed:
Jun. 07, 2021
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Chi-Lin Liu, Hsinchu, TW;
Jerry Chang-Jui Kao, Hsinchu, TW;
Wei-Hsiang Ma, Hsinchu, TW;
Lee-Chung Lu, Hsinchu, TW;
Fong-Yuan Chang, Hsinchu, TW;
Sheng-Hsiung Chen, Hsinchu, TW;
Shang-Chih Hsieh, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A logic circuit including first and second inverters, first and second NAND circuits, a transmission gate, and a transmission-gate-substitute (TGS) circuit, and wherein: for each of the first and second NAND circuits, a first input is configured to receive corresponding first and second data signals, and a second input is configured to receive an enable signal; the first inverter is configured to receive an output of the first NAND circuit; the transmission gate and the TGS circuit are arranged as a combination circuit which is configured to receive an output of the second NAND circuit as a data input, and outputs of the first inverter and the second NAND circuit as control inputs; the second inverter is configured to receive an output of the combination circuit; and an output of the second inverter represents one of an enable XOR (EXOR) function or an enable XNR (EXNR) function.