The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2023
Filed:
Sep. 25, 2018
Intel Corporation, Santa Clara, CA (US);
Abhishek Sharma, Hillsboro, OR (US);
Gregory Chen, Portland, OR (US);
Phil Knag, Hillsboro, OR (US);
Ram Krishnamurthy, Portland, OR (US);
Raghavan Kumar, Hillsboro, OR (US);
Sasikanth Manipatruni, Portland, OR (US);
Amrita Mathuriya, Portland, OR (US);
Huseyin Sumbul, Portland, OR (US);
Ian A. Young, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments herein describe techniques for a semiconductor device including a RRAM memory cell. The RRAM memory cell includes a FinFET transistor and a RRAM storage cell. The FinFET transistor includes a fin structure on a substrate, where the fin structure includes a channel region, a source region, and a drain region. An epitaxial layer is around the source region or the drain region. A RRAM storage stack is wrapped around a surface of the epitaxial layer. The RRAM storage stack includes a resistive switching material layer in contact and wrapped around the surface of the epitaxial layer, and a contact electrode in contact and wrapped around a surface of the resistive switching material layer. The epitaxial layer, the resistive switching material layer, and the contact electrode form a RRAM storage cell. Other embodiments may be described and/or claimed.