The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2023

Filed:

Jul. 09, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Amit Kumar Jain, Portland, OR (US);

Sameer Shekhar, Portland, OR (US);

Chin Lee Kuan, Bentong, MY;

Kevin Joseph Doran, North Plains, OR (US);

Dong-Ho Han, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 49/02 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5381 (2013.01); H01L 23/5383 (2013.01); H01L 28/20 (2013.01); H01L 28/40 (2013.01); H01L 23/5384 (2013.01); H01L 24/16 (2013.01); H01L 2224/16225 (2013.01);
Abstract

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.


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