The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2023

Filed:

Jun. 16, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Donguk Kwon, Asan-si, KR;

Jiwon Shin, Daejeon, KR;

Kwangbok Woo, Cheonan-si, KR;

Minseung Ji, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/32 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49833 (2013.01); H01L 23/3121 (2013.01); H01L 23/32 (2013.01); H01L 23/49816 (2013.01); H01L 24/16 (2013.01); H01L 24/73 (2013.01); H01L 25/105 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32227 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01);
Abstract

A lower semiconductor package of a package-on-package type semiconductor package includes: a package substrate; a semiconductor chip mounted on the package substrate; a chip connecting terminal disposed between the semiconductor chip and the package substrate and configured to connect the semiconductor chip to the package substrate; conductive pillars arranged on the package substrate to at least partially surround the semiconductor chip; and a dam structure configured to cover the conductive pillars on the package substrate and having a first opening at least partially surrounding the semiconductor chip.


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