The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2023

Filed:

Jan. 18, 2022
Applicant:

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Nitin Chawla, Noida, IN;

Tanmoy Roy, Greater Noida, IN;

Anuj Grover, New Delhi, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G06F 9/50 (2006.01); G11C 29/00 (2006.01); G11C 29/26 (2006.01); G11C 29/44 (2006.01); G06N 3/063 (2023.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G06F 9/5016 (2013.01); G06N 3/063 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0069 (2013.01); G11C 29/006 (2013.01); G11C 29/26 (2013.01); G11C 2029/4402 (2013.01); G11C 2211/561 (2013.01);
Abstract

A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.


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