The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2023
Filed:
May. 23, 2022
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Danping Peng, Fremont, CA (US);
Junjiang Lei, Fremont, CA (US);
Daniel Beylkin, San Jose, CA (US);
Kenneth Lik Kin Ho, Redwood City, CA (US);
Sagar Trivedi, Santa Clara, CA (US);
Fangbo Xu, San Jose, CA (US);
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD, Hsinchu, TW;
Abstract
Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.