Fin field-effect transistor (finfet) static random access memory (sram) having pass-gate transistors with offset gate contact regions

Abstract

Certain aspects are directed to a static random access memory (SRAM) including an SRAM cell with a pass-gate (PG) transistor having increased threshold voltage to improve the read margin of the SRAM cell. The SRAM generally includes a first SRAM cell having a pull-down (PD) transistor and a PG transistor coupled to the PD transistor. In certain aspects, the SRAM includes a second SRAM cell, the second SRAM cell being adjacent to the first SRAM cell and having a PD transistor and a PG transistor coupled to the PD transistor of the second SRAM cell. The SRAM may also include a gate contact region coupled to a gate region of the PG transistor of the first SRAM cell, wherein at least a portion of the gate contact region is offset from a midpoint between the first SRAM cell and the second SRAM cell.