The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2023
Filed:
Feb. 08, 2021
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Chun Chieh Wang, Kaohsiung, TW;
Yueh-Ching Pai, Taichung, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/417 (2006.01); H01L 29/49 (2006.01); H01L 21/28 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/285 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42376 (2013.01); H01L 21/28088 (2013.01); H01L 21/28114 (2013.01); H01L 21/28518 (2013.01); H01L 21/823437 (2013.01); H01L 29/0847 (2013.01); H01L 29/41791 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract
In a method of manufacturing a semiconductor device, a gate space is formed by removing a sacrificial gate electrode, a gate dielectric layer is formed in the gate space, conductive layers are formed on the gate dielectric layer to fully fill the gate space, the gate dielectric layer and the conducive layers are recessed to form a recessed gate electrode, and a contact metal layer is formed on the recessed gate electrode. The recessed gate electrode does not includes tungsten, and the contact metal layer includes tungsten.