The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2023

Filed:

May. 18, 2021
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Hung-Chih Tan, Kaohsiung, TW;

Hsing-Chao Liu, Jhudong Township, Hsinchu County, TW;

Chih-Cherng Liao, Jhudong Township, TW;

Hsiao-Ying Yang, Hsinchu, TW;

Kai-Chuan Kan, Hsinchu, TW;

Jing-Da Li, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2012.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1095 (2013.01); H01L 29/6656 (2013.01); H01L 29/66636 (2013.01);
Abstract

A method for forming a semiconductor structure includes providing a substrate including a first region with a first gate structure and a second region with a second gate structure. First to third dielectric layers are formed on the substrate. The third dielectric layer is patterned to form a first portion in the first region and a second portion in the second region. The second region is covered and at least a portion of the first portion is removed to form a first mask. The second dielectric layer is pattern by using the first mask and the second portion as the second mask to expose a portion of the first dielectric layer. The portion of the first dielectric layer is removed to form a first stacked spacer on the first gate structure and a second stacked spacer on the second gate structure.


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