The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2023

Filed:

Sep. 23, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Christopher J Waskiewicz, Rexford, NY (US);

Alexander Reznicek, Troy, NY (US);

Su Chen Fan, Cohoes, NY (US);

Heng Wu, Guilderland, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 29/0649 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract

A semiconductor device includes first and second vertical transport field-effect transistor (VTFET) devices. Each of the first and second VTFET devices includes a bottom epitaxial layer, a plurality of channel fins formed on the bottom epitaxial layer, a first interlayer dielectric (ILD) layer formed between the channel fins, a high-κ metal gate formed between the channel fins and the first ILD layer, a top epitaxial layer formed discretely on each of the channel fins, and a trench epitaxial layer formed continuously across the top epitaxial layer, a portion of the first ILD layer also being formed between the first and second VTFET device. The semiconductor device also includes a second ILD layer formed on the portion of the first ILD layer that is between the first and second VTFET devices, the second ILD layer separating the top epitaxial layers of the first and second VTFET devices.


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