The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2023

Filed:

Jul. 15, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Inchan Hwang, Schenectady, NY (US);

Hwichan Jun, Clifton Park, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/822 (2006.01); H01L 27/085 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/085 (2013.01); H01L 21/8221 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01);
Abstract

An array of multi-stack transistor structures is provided, wherein the multi-stack transistor structures are arranged in a plurality of rows and a plurality of columns in the array, wherein each of the multi-stack transistor structures includes two or more vertically arranged transistor stacks, and wherein a dam structure is formed between adjacent two rows in a same column so that a multi-stack transistor structure in one of the adjacent two rows is electrically isolated from a multi-stack transistor structure in the other of the adjacent two rows in the same column.


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Hwang, Inchan. (2023). Method of forming an array of multi-stack nanosheet structures having a dam structure isolating multi-stack transistors (U.S. Patent No. 11742345). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11742345

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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