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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11742246 B1

PDFFull Text
Date of Patent:
Aug. 29, 2023

Filed:

Oct. 15, 2021

Local isolation of source/drain for reducing parasitic capacitance in vertical field effect transistors

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Hemanth Jagannathan, Niskayuna, NY (US);

Christopher J. Waskiewicz, Rexford, NY (US);

Alexander Reznicek, Troy, NY (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorneys:

Fleit Intellectual Property Law

Thomas S. Grzesik

Primary Examiner:

Victor A Mandala

Assistant Examiner:

Lawrence C Tynes, Jr

Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823481 (2013.01); H01L 21/76224 (2013.01); H01L 21/823487 (2013.01); H01L 27/088 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01);
Abstract

A vertical field effect transistor structure and method for fabricating the same. The structure includes a source/drain layer in contact with at least one semiconductor fin. An edge portion of the source/drain layer includes a notched region filled with a dielectric material. A spacer layer includes a first portion in contact with the source/drain layer and a second portion in contact with the dielectric material. A gate structure contacts the spacer layer and the dielectric material. The method includes forming a source/drain layer in contact with at least one semiconductor fin. A spacer layer is formed in contact with the source/drain layer. A portion of the spacer layer is removed to expose an end portion of the source/drain layer. The exposed end portion of the source/drain layer is recessed to form a notched region within the source/drain layer. A dielectric layer is formed within the notched region.

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