The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 22, 2023
Filed:
May. 11, 2021
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Luigi Pilolli, L'Aquila, IT;
Ali Feiz Zarrin Ghalam, Sunnyvale, CA (US);
Guan Wang, San Jose, CA (US);
Qiang Tang, Cupertino, CA (US);
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 16/32 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0632 (2013.01); G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/32 (2013.01);
Abstract
A memory device includes a plurality of input/output (I/O) nodes, a circuit, a latch, a memory, and control logic. The plurality of I/O nodes receive a predefined data pattern. The circuit adjusts a delay for each I/O node as the predefined data pattern is received. The latch latches the data received on each I/O node. The memory stores the latched data. The control logic compares the stored latched data to an expected data pattern and sets the delay for each I/O node based on the comparison.