The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2023
Filed:
Dec. 14, 2020
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01); H01L 27/092 (2006.01); H01L 21/3205 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/0262 (2013.01); H01L 21/02359 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02645 (2013.01); H01L 21/02664 (2013.01); H01L 21/32055 (2013.01); H01L 21/32137 (2013.01); H01L 21/823821 (2013.01); H01L 21/823864 (2013.01); H01L 27/0924 (2013.01); H01L 29/66795 (2013.01);
Abstract
A method for forming a semiconductor device and a semiconductor device formed by the method are disclosed. In an embodiment, the method includes depositing a dummy dielectric layer on a fin extending from a substrate; depositing a dummy gate seed layer on the dummy dielectric layer; reflowing the dummy gate seed layer; etching the dummy gate seed layer; and selectively depositing a dummy gate material over the dummy gate seed layer, the dummy gate material and the dummy gate seed layer constituting a dummy gate.