The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2023

Filed:

Mar. 24, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Te-Chih Hsiung, Taipei, TW;

Jyun-De Wu, New Taipei, TW;

Peng Wang, Hsinchu, TW;

Huan-Just Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/48 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76831 (2013.01); H01L 21/486 (2013.01); H01L 21/76802 (2013.01); H01L 21/76883 (2013.01); H01L 21/76895 (2013.01); H01L 21/76897 (2013.01); H01L 23/5221 (2013.01); H01L 29/41791 (2013.01); H01L 29/785 (2013.01);
Abstract

A method includes depositing a dielectric cap over a gate structure. A source/drain contact is formed over a source/drain region after forming the dielectric cap. A top of the dielectric cap is doped to form a doped region in the dielectric cap. After doping the top of the dielectric cap, a etch stop layer and an interlayer dielectric (ILD) layer are deposited over the dielectric cap. A via opening is formed to extend though the ILD layer and the etch stop layer to expose the source/drain contact. A source/drain via is filled in the via opening.


Find Patent Forward Citations

Loading…