The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2023

Filed:

Aug. 17, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Tomoko Ogura Iwasaki, San Jose, CA (US);

Avani F. Trivedi, Eagle, ID (US);

Jianmin Huang, San Carlos, CA (US);

Aparna U. Limaye, Boise, ID (US);

Tracy D. Evans, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G06F 11/07 (2006.01); G06F 11/30 (2006.01); G06F 12/02 (2006.01); G06F 11/20 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06F 11/0772 (2013.01); G06F 11/203 (2013.01); G06F 11/3037 (2013.01); G06F 12/0246 (2013.01); G06F 12/0253 (2013.01); G06F 2212/7209 (2013.01);
Abstract

Systems, apparatuses, and methods related to media management, including 'garbage collection,' in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a signaling can be received that indicates a request from a controller to migrate valid data from a first data block to a second data block. For example, the first data block can be a data block of a plurality of memory cells configured as single-level-cell (SLC) memory. The second data block can be configured as multi-level-cell (MLC) memory. The data migration operation can include an error control operation that is performed using the memory component, the error control operation excluding transferring the data to the controller. The data can be migrated from the first data block configured as SLC memory to the second data block configured as MLC memory after the error control operation is performed using the memory component.


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