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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11721757 B1

PDFFull Text
Date of Patent:
Aug. 08, 2023

Filed:

Aug. 02, 2021

Semiconductor device

Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Purakh Raj Verma, Singapore, SG;

Chia-Huei Lin, Hsinchu, TW;

Kuo-Yuh Yang, Hsinchu County, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;

Attorney:

Winston Hsu

Primary Examiner:

Benjamin Tzu-Hung Liu

Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 21/266 (2006.01); H01L 21/285 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7824 (2013.01); H01L 29/0696 (2013.01); H01L 29/1095 (2013.01); H01L 29/4238 (2013.01); H01L 29/66681 (2013.01); H01L 29/78624 (2013.01); H01L 21/266 (2013.01); H01L 21/28518 (2013.01); H01L 29/665 (2013.01);
Abstract

A LDMOS device includes a semiconductor layer on an insulation layer and a ring shape gate on the semiconductor layer. The ring shape gate includes a first gate portion, a second gate portion, and two third gate portions connecting the first gate portion and the second gate portion. The semiconductor device further includes a first drain region and a second drain region formed in the semiconductor layer at two sides of the ring shape gate, a plurality of source regions formed in the semiconductor layer surrounded by the ring shape gate, a plurality of body contact regions formed in the semiconductor layer and arranged between the source regions, and a first body implant region and a second body implant region formed in the semiconductor layer, respectively underlying part of the first gate portion and part of the second gate portion, and being connected by the body contact regions.

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