The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2023

Filed:

Oct. 28, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventor:

Sri Chaitra Jyotsna Chavali, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 21/486 (2013.01); H01L 21/4846 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/5381 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/562 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/351 (2013.01);
Abstract

Embodiments include a package substrate, a semiconductor package, and a method of forming the package substrate. A package substrate includes a core substrate between a first alternate core substrate and a second alternate core substrate. The first alternate core substrate includes conductive layers and vias. The package substrate includes a dielectric layer surrounding the core and first and second alternate substrates, a first conductive layer on a top surface of the dielectric layer, and a second conductive layer on top surfaces of the core and first and second alternate substrates, where the dielectric layer is over/under the core and first and second alternate substrates. The package substrate includes a third conductive layer on bottom surfaces of the core and first and second alternate substrates. The conductive layers are coupled to the vias within the first alternate core substrate, where the conductive layers and vias couple the second and third layers.


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