The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2023

Filed:

Jul. 14, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Nak-jin Son, Suwon-si, KR;

Dong-il Bae, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); B82Y 10/00 (2011.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 29/0673 (2013.01); H01L 29/1033 (2013.01); H01L 29/42392 (2013.01); B82Y 10/00 (2013.01);
Abstract

An integrated circuit device includes: a fin-type active area including a fin top surface on a top portion and an anti-punch-through recess having a lowermost level lower than a level of the fin top surface; a nanosheet stack facing the fin top surface, the nanosheet stack including a plurality of nanosheets having vertical distances different from each other from the fin top surface; a gate structure surrounding each of the plurality of nanosheets; a source/drain region having a side wall facing at least one of the plurality of nanosheets; and an anti-punch-through semiconductor layer including a first portion filling the anti-punch-through recess, and a second portion being in contact with a side wall of a first nanosheet most adjacent to the fin-type active area among the plurality of nanosheets, the anti-punch-through semiconductor layer including a material different from a material of the source/drain region.


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