The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2023

Filed:

May. 26, 2022
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Zhi-Cheng Lee, Tainan, TW;

Wei-Jen Chen, Tainan, TW;

Kai-Lin Lee, Kinmen County, TW;

Tai-Ju Chen, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6659 (2013.01); H01L 29/0642 (2013.01); H01L 29/66681 (2013.01);
Abstract

A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.


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