The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2023

Filed:

Dec. 20, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chang-Chih Huang, Taichung, TW;

Jui-Yu Pan, Neipu Township, TW;

Kuo-Chyuan Tzeng, Chu-Pei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H10B 63/00 (2023.01); G11C 11/56 (2006.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
G11C 13/0028 (2013.01); G11C 11/56 (2013.01); G11C 13/0026 (2013.01); H10B 63/20 (2023.02); H10B 63/80 (2023.02); H10B 63/84 (2023.02); H10N 70/063 (2023.02); H10N 70/8265 (2023.02);
Abstract

Various embodiments of the present application are directed towards a method for forming an integrated chip. The method includes forming a dielectric structure over a substrate. A first conductive wire is formed along the dielectric structure. The first conductive wire extends laterally along a first direction. A memory stack is formed on a top surface of the first conductive wire. A second conductive wire is formed over the memory stack. The second conductive wire extends laterally along a second direction orthogonal to the first direction. An upper conductive via is formed on the top surface of the first conductive wire. An upper surface of the upper conductive via is above the second conductive wire.


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