The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 25, 2023
Filed:
Mar. 03, 2020
Qualcomm Incorporated, San Diego, CA (US);
Hyeokjin Lim, San Diego, CA (US);
Bharani Chava, Cork City, IE;
Foua Vang, Sacramento, CA (US);
Seung Hyuk Kang, San Diego, CA (US);
Venugopal Boynapalli, San Marcos, CA (US);
QUALCOMM INCORPORATED, San Diego, CA (US);
Abstract
A MOS IC logic cell includes a plurality of gate interconnects extending on tracks in a first direction. The logic cell includes intra-cell routing interconnects coupled to at least a subset of the gate interconnects. The intra-cell routing interconnects include intra-cell Mx layer interconnects on an Mx layer extending in the first direction. The Mx layer is a lowest metal layer for PG extending in the first direction. The intra-cell Mx layer interconnects extend in the first direction over at least a subset of the tracks excluding every mtrack, where 2≤m<Pand Pis a PG grid pitch. A MOS IC may include at least one MOS IC logic cell, and may further include a first set of PG Mx layer interconnects extending in the first direction over the at least one logic cell. The first set of PG Mx layer interconnects have the pitch P>m*P.