The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 18, 2023
Filed:
Feb. 19, 2021
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
David Ross Economy, Boise, ID (US);
Rita J. Klein, Boise, ID (US);
Jordan D. Greenlee, Boise, ID (US);
John Mark Meldrim, Boise, ID (US);
Brenda D. Kraus, Boise, ID (US);
Everett A. McTeer, Eagle, ID (US);
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 27/11519 (2017.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); H01L 27/11565 (2017.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 41/35 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H01L 29/4966 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 41/35 (2023.02); H10B 43/35 (2023.02);
Abstract
Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.