The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2023

Filed:

May. 18, 2021
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Wei-Sheng Lei, San Jose, CA (US);

Kurtis Leschkies, San Jose, CA (US);

Roman Gouk, San Jose, CA (US);

Giback Park, San Jose, CA (US);

Kyuil Cho, Santa Clara, CA (US);

Tapash Chakraborty, Maharashtra, IN;

Han-Wen Chen, Cupertino, CA (US);

Steven Verhaverbeke, San Francisco, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76825 (2013.01); H01L 21/486 (2013.01); H01L 21/76877 (2013.01);
Abstract

The present disclosure relates to micro-via structures for interconnects in advanced wafer level semiconductor packaging. The methods described herein enable the formation of high-quality, low-aspect-ratio micro-via structures with improved uniformity, thus facilitating thin and small-form-factor semiconductor devices having high I/O density with improved bandwidth and power.


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