The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2023

Filed:

Dec. 11, 2020
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Martin Poelzl, Ossiach, AT;

Oliver Blank, Villach, AT;

Franz Hirler, Isen, DE;

Maximilian Roesch, St. Magdalen, AT;

Li Juin Yip, Villach, AT;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/739 (2006.01); H01L 21/308 (2006.01); H01L 29/417 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/407 (2013.01); H01L 21/3086 (2013.01); H01L 29/404 (2013.01); H01L 29/41766 (2013.01); H01L 29/4236 (2013.01); H01L 29/66348 (2013.01); H01L 29/66719 (2013.01); H01L 29/66727 (2013.01); H01L 29/66734 (2013.01); H01L 29/7397 (2013.01); H01L 29/7813 (2013.01); H01L 29/0696 (2013.01); H01L 29/7811 (2013.01);
Abstract

A semiconductor device includes a gate structure extending from a first surface of a semiconductor portion into a mesa section between neighboring field electrode structures and an alignment layer formed on the first surface. The alignment layer includes mask pits formed in the alignment layer in a vertical projection of the field electrode structures. Sidewalls of the mask pits have a smaller tilt angle with respect to the first surface than sidewalls of the field electrode structures. The gate structure is in the vertical projection of a gap between neighboring mask pits.


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