The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2023

Filed:

Sep. 13, 2022
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chun-Hung Chen, Tainan, TW;

Ming-Tse Lin, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/08 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/64 (2006.01); H01L 23/48 (2006.01); H01L 21/48 (2006.01); H01L 27/01 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/486 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/49827 (2013.01); H01L 23/642 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 27/01 (2013.01); H01L 2224/13023 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/16113 (2013.01); H01L 2224/16147 (2013.01);
Abstract

A semiconductor structure includes an interposer substrate having an upper surface, a lower surface opposite to the upper surface, and a device region. A first redistribution layer is formed on the upper surface of the interposer substrate. A guard ring is formed in the interposer substrate and surrounds the device region. At least a through-silicon via (TSV) is formed in the interposer substrate. An end of the guard ring and an end of the TSV that are near the upper surface of the interposer substrate are flush with each other, and are electrically connected to the first redistribution layer.


Find Patent Forward Citations

Loading…