The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 27, 2023
Filed:
Aug. 06, 2020
Micron Technology, Inc., Boise, ID (US);
Harish Reddy Singidi, Fremont, CA (US);
Scott Anthony Stoller, Boise, ID (US);
Jung Sheng Hoei, Newark, CA (US);
Ashutosh Malshe, Fremont, CA (US);
Gianni Stephen Alsasua, Rancho Cordova, CA (US);
Kishore Kumar Muchherla, Fremont, CA (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
NAND memory devices are described that utilize higher read-margin cell types to provide a more granular read disturb indicator without utilizing dummy cells. For example, a NAND architecture may have some cells that are configured as SLC or MLC cells. SLC or MLC cells have more read disturb margin—that is these cells can withstand more read disturb current leakage into the cell before a bit error occurs than TLC or QLC cells. These higher margin cells may serve as the read disturb indicator for a group of cells that have a comparatively lower read disturb margin. Since there are more pages of these higher margin cells than there are pages of dummy cells, these indicators may serve a smaller group of pages than the dummy pages. This reduces the time needed to complete a read disturb scan as fewer pages need to be scanned.