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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11688469 B1

PDFFull Text
Date of Patent:
Jun. 27, 2023

Filed:

Aug. 11, 2021

Non-volatile memory with sub-block based self-boosting scheme

Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Dengtao Zhao, Santa Clara, CA (US);

Gerrit Jan Hemink, San Ramon, CA (US);

Xiang Yang, Santa Clara, CA (US);

Ken Oowada, Fujisawa, JP;

Guirong Liang, Santa Clara, CA (US);

Assignee:

SanDisk Technologies LLC, Addison, TX (US);

Attorney:

Vierra Magen Marcus LLP

Primary Examiner:

Tha-O H Bui

Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/34 (2006.01); H01L 25/18 (2023.01); H01L 23/00 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01); G11C 16/24 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
G11C 16/3427 (2013.01); G11C 11/5628 (2013.01); G11C 11/5635 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/16 (2013.01); G11C 16/24 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/08145 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06562 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01);
Abstract

To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.

Find Patent Forward Citations

Zhao, Dengtao. (2023). Non-volatile memory with sub-block based self-boosting scheme (U.S. Patent No. 11688469). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11688469

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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