The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2023

Filed:

Jun. 14, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Zhengang Chen, San Jose, CA (US);

Sai Krishna Mylavarapu, Folsom, CA (US);

Zhenlei Shen, Milpitas, CA (US);

Tingjun Xie, Milpitas, CA (US);

Charles S. Kwong, Redwood City, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 29/52 (2006.01); G06F 11/10 (2006.01); G11C 16/26 (2006.01); G11C 29/42 (2006.01); G06F 11/07 (2006.01); G06F 11/14 (2006.01); G11C 29/44 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3404 (2013.01); G06F 11/076 (2013.01); G06F 11/1048 (2013.01); G06F 11/1068 (2013.01); G06F 11/141 (2013.01); G11C 16/26 (2013.01); G11C 29/42 (2013.01); G11C 29/44 (2013.01); G11C 29/52 (2013.01); G06F 2201/81 (2013.01); G11C 2029/0411 (2013.01);
Abstract

Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device determines that a bit error rate (BER) corresponding to a read operation to read a unit of data in a memory component satisfies a threshold criterion, determines a write-to-read (W2R) delay for the read operation, wherein the W2R delay comprises a difference between a time of the read operation and a write timestamp indicating when the unit of data was written to the memory component, and determines whether the W2R delay is within a W2R delay range corresponding to an initial read voltage level used by the read operation to read the unit of data. The processing device initiates a defect detection operation responsive to the W2R delay being within the W2R delay range, the defect detection operation to detect time-varying defects in the memory component.


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