The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

Jun. 12, 2020
Applicant:

SK Hynix Inc., Icheon-si Gyeonggi-do, KR;

Inventors:

Ju Il Eom, Yongin-si Gyeonggi-do, KR;

Jae Hoon Lee, Icheon-si Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Icheon-si Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5385 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 24/06 (2013.01); H01L 24/13 (2013.01); H01L 24/45 (2013.01); H01L 24/73 (2013.01); H01L 25/18 (2013.01); H01L 2224/73101 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01);
Abstract

A semiconductor package includes a package substrate, a lower chip, an interposer, and an upper chip which are stacked on the package substrate, and bonding wires electrically connecting the lower chip to the package substrate. The lower chip includes first and second lower chip pads spaced apart from each other on an upper surface of the lower chip, wire bonding pads bonded to the bonding wires on the upper surface of the lower chip, and lower chip redistribution lines electrically connecting the second lower chip pad to the wire bonding pad. The interposer includes an upper chip connection pad on an upper surface of the interposer, a lower chip connection pad on a lower surface of the interposer, and a through via electrode electrically connecting the upper chip connection pad to the lower chip connection pad.


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