The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

Apr. 11, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Fang-Yu Liang, Taipei, TW;

Kai-Chiang Wu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/528 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/566 (2013.01); H01L 21/76805 (2013.01); H01L 23/3142 (2013.01); H01L 23/5283 (2013.01); H01L 23/53295 (2013.01);
Abstract

A package component, a semiconductor package and a manufacturing method thereof are provided. The package component for electrically coupling a semiconductor die includes a functional circuit structure and a seal ring structure embedded in an insulating layer. The semiconductor die disposed on the package component is electrically coupled to the functional circuit structure. The seal ring structure is electrically isolated from the functional circuit structure, the seal ring structure includes a stack of alternating interconnect layers and via patterns, the via pattern at each level of the stack includes first features spaced apart from one another and arranged at neighboring corners of the insulating layer, and the first features are offset lengthwise relative to each other to overlap therewith, and the first features are spaced apart widthwise relative to each other.


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