The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

Jun. 28, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Zhiguo Qian, Chandler, AZ (US);

Kaladhar Radhakrishnan, Chandler, AZ (US);

Kemal Aygun, Tempe, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/49 (2006.01); H01L 23/64 (2006.01); H01L 23/498 (2006.01); H01L 21/68 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49816 (2013.01); H01L 21/4853 (2013.01); H01L 21/68 (2013.01); H01L 23/49827 (2013.01); H01L 24/17 (2013.01); H01L 23/5384 (2013.01); H01L 2224/08165 (2013.01); H01L 2224/16157 (2013.01); H01L 2224/16165 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/24221 (2013.01); H01L 2224/32165 (2013.01); H01L 2224/32235 (2013.01); H01L 2224/73103 (2013.01); H01L 2224/73104 (2013.01); H01L 2224/73153 (2013.01); H01L 2224/73203 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73209 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/30111 (2013.01);
Abstract

The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.


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