The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2023

Filed:

Jul. 14, 2021
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Yao-Ting Tsai, Taichung, TW;

Hsiu-Han Liao, Taichung, TW;

Che-Fu Chuang, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H10B 41/42 (2023.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H10B 41/30 (2023.01);
U.S. Cl.
CPC ...
H10B 41/42 (2023.02); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01); H10B 41/30 (2023.02);
Abstract

Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.


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